Simulation · 2026 · Independent Study
High-Frequency Trading Architecture Exploration via Neuromorphic Alternatives
Quantitative FinanceSNNHardware AccelerationL2 Order Book Data
§ I
Abstract
Investigates whether event-driven spiking networks can encode limit-order-book updates natively as spike trains, exploiting their temporal sparsity to reduce inference latency relative to conventional FPGA MAC pipelines.
§ II
System Architecture
L2 book snapshots → delta-encoding into temporal spike trains → MSNN population coding → readout via linear decoder for short-horizon mid-price direction.
§ III
Results
Simulated latency envelope of 1.8–4.1 μs per update on a modeled MSNN substrate; competitive AUC on 100 ms horizon.